bus ، device و ‘…

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● Computer Buses
● Bus Width
● Bus Clocking
● Bus Arbitration
● Bus Operations

نوع زبان: انگلیسی حجم: 0.23 مگا بایت
نوع فایل: اسلاید پاورپوینت تعداد اسلایدها: 29 صفحه
سطح مطلب: نامشخص پسوند فایل: pptx
گروه موضوعی: زمان استخراج مطلب: 2019/06/07 11:40:30

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عبارات مهم استفاده شده در این مطلب

عبارات مهم استفاده شده در این مطلب

bus, ., device, line, ‘, memory, cycle, master, datum, address, computer, pc,

توجه: این مطلب در تاریخ 2019/06/07 11:40:30 به صورت خودکار از فضای وب آشکار توسط موتور جستجوی پاورپوینت جمع آوری شده است و در صورت اعلام عدم رضایت تهیه کننده ی آن، طبق قوانین سایت از روی وب گاه حذف خواهد شد. این مطلب از وب سایت زیر استخراج شده است و مسئولیت انتشار آن با منبع اصلی است.

http://grail.cba.csuohio.edu/~arndt/cis-480/notes/cis480-8.pptx

در صورتی که محتوای فایل ارائه شده با عنوان مطلب سازگار نبود یا مطلب مذکور خلاف قوانین کشور بود لطفا در بخش دیدگاه (در پایین صفحه) به ما اطلاع دهید تا بعد از بررسی در کوتاه ترین زمان نسبت به حدف با اصلاح آن اقدام نماییم. جهت جستجوی پاورپوینت های بیشتر بر روی اینجا کلیک کنید.

عبارات پرتکرار و مهم در این اسلاید عبارتند از: bus, ., device, line, ‘, memory, cycle, master, datum, address, computer, pc,

مشاهده محتوای متنیِ این اسلاید ppt

مشاهده محتوای متنیِ این اسلاید ppt

computer buses a bus is a common electrical pathway between multiple devices. can be internal to the cpu to transport data to and from the alu. can be external to the cpu to connect it to memory or to i o devices. early pcs had a single external bus or system bus. modern pcs have a special purpose bus between the cpu and memory and at least one other bus for the i o devices. computer buses computer buses in order to make it possible for boards designed by third parties to attach to the system bus there must be well defined rules about how the bus works and which all attached devices must obey. these rules are called the bus protocol. in addition there must be mechanical and electrical specifications. computer buses a number of buses are in widespread use in the computer world. multibus ۸ ۸۶ ibm pc pc xt isa bus pc at eisa bus ۸ ۳۸۶ microchannel ps ۲ pci bus many pcs nubus macintosh universal serial bus modern pcs firewire consumer electronics computer buses some devices that attach to a bus are active and can initiate bus transfers. they are called masters. some devices are passive and wait for requests. they are called slaves. some devices may act as slaves at some times and masters at others. memory can never be a master device. computer buses the binary signals that computer devices output are frequently not strong enough to power a chip. the bus may be relatively long or have several devices attached to it. most bus masters are connected to the bus by a chip called a bus driver which is essentially a digital amplifier. most slaves are connected to the bus by a bus receiver. computer buses for devices which can be both master and slave a device called a bus transceiver is used. these bus interface devices are often tri state devices to allow them to disconnect when they are not needed. a bus has address data and control lines but there is not necessarily a one to one mapping between cpu pins and bus lines. a decoder chip between cpu and bus would be needed in this case. bus width the more address lines a bus has the more memory the cpu can address directly. if a bus has n address lines then the cpu can use it to address ۲n different memory locations. larger buses are more expensive they need more wires they take up more space on the motherboard they need bigger connectors early pc buses did not contain enough address lines leading several backward compatible upgrades to the bus. bus width bus width the number of data lines needed also tends to increase over time. there are two ways to increase the data bandwidth of a bus decrease the bus cycle time increase the data bus width speeding up the bus results in problems of bus skew since data on individual lines travel at slightly different speeds. this also makes the bus non compatible with pre existing devices. bus width therefore an increased data width is the usual answer e.g. in the pc which went from ۸ data lines to ۱۶ and then to ۳۲ on essentially the same bus . another solution is to use a multiplexed bus. the same lines are used for both data and addressing by breaking up the bus operation into multiple steps. this slows down bus performance. bus clocking buses can be divided up into two categories depending on their clocking. a synchronous bus has a line driven by a crystal oscillator. the signal on this line consists of a square wave with a frequency of ۵ ۱ mhz. all bus activities take an integral number of these cycles called bus cycles. the asynchronous bus does not have a master clock. bus cycles can be of any length required and need not be the same. bus clocking consider a synchronous bus with a ۴ mhz clock which gives a clock cycle of ۲۵ nsec. assume reading from memory takes ۴ nsec from the time the address is stable. it takes three bus cycles to read a word. mreq’ indicates that memory is being accessed. rd’ is asserted for reads and negated for writes. wait’ inserts wait states extra bus cycles until the memory is finished bus clocking bus clocking although synchronous buses are easy to work with due to their discrete time intervals they also have some problems. everything works in multiples of the bus clock. if a cpu and memory can complete a transfer in ۳.۱ cycles they have to stretch it to ۴. because fractional cycles are forbidden. once a bus cycle has been chosen and memory and i o cards have been built for it it is difficult to take advantage of future improvements in technology. the bus has to be geared to the slowest devices legacy devices on the bus. bus clocking mixed technology can be handled by going to an asynchronous bus. the master device asserts mreq’ rd’ etc. and then asserts msyn’ master synchronization . seeing this the slave device starts to work. when it is finished it asserts ssyn’ slave synchronization . seeing this the master reads the data. when it is done it negates mreq’ rd’ the address lines msyn’ and ssyn’. bus clocking this ends the read. a set of signals that interlocks in this way is called a full handshake. full handshakes are timing independent. each event is caused by a prior event not by a clock cycle. despite the advantages of asynchronous buses most buses are synchronous since they are easier to build and since there is such a large investment in synchronous bus technology. bus clocking bus arbitration i o chips have to become bus master to read and write memory and to cause interrupts. if two or more devices want to become bus master at the same time a bus arbitration mechanism is needed. arbitration mechanisms can be centralized or decentralized. a simple …

کلمات کلیدی پرکاربرد در این اسلاید پاورپوینت: bus, ., device, line, ‘, memory, cycle, master, datum, address, computer, pc,

این فایل پاورپوینت شامل 29 اسلاید و به زبان انگلیسی و حجم آن 0.23 مگا بایت است. نوع قالب فایل pptx بوده که با این لینک قابل دانلود است. این مطلب برگرفته از سایت زیر است و مسئولیت انتشار آن با منبع اصلی می باشد که در تاریخ 2019/06/07 11:40:30 استخراج شده است.

http://grail.cba.csuohio.edu/~arndt/cis-480/notes/cis480-8.pptx

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