Scalar Unpipelined Processor

فهرست عناوین اصلی در این پاورپوینت

فهرست عناوین اصلی در این پاورپوینت

● During This Lecture
● General Performance Metrics
● Scalar Unpipelined Processor
● Pipelined Processor
● Example of a Six-Stage Pipelined Processor
● Pipelining & Performance
● Super-Pipelining Processor
● Stage Quantazation
● Superscalar machine of Degree n=3
● Superpipelined Superscalar Machine
● Characteristics of Superscalar Machines
● Limitations of Scalar Pipelines
● Deeper Pipeline, a Solution?
● Bounded Pipelines Performance
● Inefficient Unification into a Single Pipeline
● Diversified Pipelines
● Performance Lost Due to Rigid Pipelines
● Rigid Pipeline Penalty
● Out-Of-Order Execution
● From Scalar to Superscalar Pipelines
● Parallel Pipelines
● Temporal & Spatial Machine Parallelism
● Parallel Pipelines
● Parallel Pipeline’s Interconnections
● The Sequel of the i486: Pentium Microprocessor
● Pentium Microprocessor
● Diversified Pipelines
● Diversified Pipelines (3)
● Advantages of Diversified Pipelines
● Diversified Pipelines Design
● Diversified Pipelines Design (2)
● Dynamic Pipelines
● Dynamic Pipelines (2)
● Dynamic Pipelines (3)
● Pentium 4
● Pentium 4 Block Diagram
● Pentium 4 Operation
● Pentium 4 Pipeline
● Pentium 4 Pipeline Operation (1)
● Pentium 4 Pipeline Operation (2)
● Pentium 4 Pipeline Operation (3)
● Pentium 4 Pipeline Operation (4)
● Pentium 4 Pipeline Operation (5)
● Pentium 4 Pipeline Operation (6)
● Introduction to PowerPC 620

نوع زبان: انگلیسی حجم: 1.73 مگا بایت
نوع فایل: اسلاید پاورپوینت تعداد اسلایدها: 49 صفحه
سطح مطلب: نامشخص پسوند فایل: ppt
گروه موضوعی: زمان استخراج مطلب: 2019/05/16 03:06:30

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عبارات مهم استفاده شده در این مطلب

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., instruction, pipeline, stage, ۱۵, ۴۴۷, computer, architecture, fall, id, mem, wb,

توجه: این مطلب در تاریخ 2019/05/16 03:06:30 به صورت خودکار از فضای وب آشکار توسط موتور جستجوی پاورپوینت جمع آوری شده است و در صورت اعلام عدم رضایت تهیه کننده ی آن، طبق قوانین سایت از روی وب گاه حذف خواهد شد. این مطلب از وب سایت زیر استخراج شده است و مسئولیت انتشار آن با منبع اصلی است.

https://web2.qatar.cmu.edu/~msakr/15447-f08/lectures/Lecture15.ppt

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عبارات پرتکرار و مهم در این اسلاید عبارتند از: ., instruction, pipeline, stage, ۱۵, ۴۴۷, computer, architecture, fall, id, mem, wb,

مشاهده محتوای متنیِ این اسلاید ppt

مشاهده محتوای متنیِ این اسلاید ppt

۱۵ ۴۴۷ computer architecture fall ۲ ۸ october ۱۳th ۲ ۸ majd f. sakr msakr@qatar.cmu.edu www.qatar.cmu.edu ~msakr ۱۵۴۴۷ f ۸ cs ۴۴۷– computer architecture lecture ۱۵ superscalar processors greet class ۱۵ ۴۴۷ computer architecture fall ۲ ۸ during this lecture introduction to superscalar pipelined processors limitations of scalar pipelines from scalar to superscalar pipelines superscalar pipeline overview ۱۵ ۴۴۷ computer architecture fall ۲ ۸ general performance metrics performance is determined by ۱ instruction count ۲ clock rate ۳ cpi –clocks per instructions. exe time instruction count cpi cycle time the instruction count is governed by compiler’s techniques architectural decisions the cpi is primarily governed by architectural decisions. the cycle time is governed by technology improvements architectural decisions. ۱۵ ۴۴۷ computer architecture fall ۲ ۸ scalar unpipelined processor only one instruction can be resident at the processor at any given time. the whole processor is considered as one stage k ۱. cpi ۱ ipc one instruction resident in processor the number of stages k ۱ ۱۵ ۴۴۷ computer architecture fall ۲ ۸ pipelined processor k –number of pipe stages instructions are resident at the processor at any given time. in our example k ۵ stages number of parallelism concurrent instruction in the processor is also equal to ۵. one instruction will be accomplished each clock cycle cpi ipc ۱ ۱st inst. 
۲nd inst. ۳rd inst. ۴th inst. ۵th inst. the number of stages k ۵ ideally cpi ipc ۱ ’ims k ۵ if id ex mem wb if id ex mem wb if id ex mem wb if id ex mem wb if id ex mem wb ۱۵ ۴۴۷ computer architecture fall ۲ ۸ example of a six stage pipelined processor ۱۵ ۴۴۷ computer architecture fall ۲ ۸ pipelining performance the pipeline depth is the number of stages implemented in the processor it is an architectural decision also it is directly related to the technology. in the previous example k ۵. the stall’s cpi are directly related to the code’s instructions and the density of existing dependences and branches. ideally the cpi is one. ۱۵ ۴۴۷ computer architecture fall ۲ ۸ super pipelining processor if instruction fetch requires a cache access in order to get the next instruction to be delivered to the pipeline. id instruction decode requires that the control unit decodes the instruction to know what it does. obviously the fetch stage cache access requires much more time than the decode stage –combinational logic. why not subdivide each pipe stage into m other stages of smaller amount of time required for each stage minor cycle time. ۱۵ ۴۴۷ computer architecture fall ۲ ۸ super pipelining processor the machine can issue a new instruction every minor cycle. parallelism k x m. for this figure ’ism k x m ۴ x ۳ ۱۲. super pipelined machine of degree m ۳ ۱۵ ۴۴۷ computer architecture fall ۲ ۸ stage quantazation a four stage instruction pipeline b eleven stage instruction pipeline ۱۵ ۴۴۷ computer architecture fall ۲ ۸ superscalar machine of degree n ۳ the superscalar degree is determined by the issue parallelism n the maximum number of instructions that can be issued in every machine cycle. parallelism k x n. for this figure ’ism k x n ۴ x ۳ ۱۲ is there any reason why the superscalar machine cannot also be superpipelined ۱۵ ۴۴۷ computer architecture fall ۲ ۸ superpipelined superscalar machine the superscalar degree is determined by the issue parallelism n and the sub stages m the number of stages k. parallelism k x m x n for this figure ’ism k x m x n ۵ x ۳ x ۳ ۴۵ id alu mem wb if if id alu mem wb if id alu mem wb if id alu mem wb if id alu mem wb if id alu mem wb if id alu mem wb if id alu mem wb ۱۵ ۴۴۷ computer architecture fall ۲ ۸ characteristics of superscalar machines simultaneously advance multiple instructions through the pipeline stages. multiple functional units higher instruction execution throughput. able to execute instructions in an order different from that specified by the original program. out of program order execution allows more parallel processing of instructions. ۱۵ ۴۴۷ computer architecture fall ۲ ۸ limitations of scalar pipelines instructions regardless of type traverse the same set of pipeline stages. only one instruction can be resident in each pipeline stage at any time. instructions advance through the pipeline stages in a lockstep fashion. upper bound on pipeline throughput. if id exe wb mem ۱۵ ۴۴۷ computer architecture fall ۲ ۸ deeper pipeline a solution performance is proportional to ۱ instruction count ۲ clock rate ۳ ipc –instructions per clock. deeper pipeline has fewer logic gate levels in each stage this leads to a shorter cycle time higher clock rate. but deeper pipeline can potentially incur higher penalties for dealing with inter instruction dependences. ۱۵ ۴۴۷ computer architecture fall ۲ ۸ bounded pipelines performance scalar pipeline can only initiate at most one instruction every cycle hence ipc is fundamentally bounded by one. to get more instruction throughput we must initiate more than one instruction every machine cycle. hence having more than one instruction resident in each pipeline stage is necessary parallel pipeline. ۱۵ ۴۴۷ computer architecture fall ۲ ۸ inefficient unification into a single pipeline different instruction types require different sets of computations. in if id there is significant uniformity of different instruction types. if id perform their job regardless of the instruction they are woking on. ۱۵ ۴۴۷ computer architecture fall ۲ ۸ inefficient unification into a single pipeline but in execution stages alu mem there is substantial diversity. instructions that require long possibly variable latencies f.p. multiply divide are difficult to unify with simple instructions that require only a single cycle latency. add f.p. divide mult one clock cycle ten clock cycles thirty clock cycles ۱۵ ۴۴۷ computer architecture fall ۲ ۸ diversified pipelines specialized execution units customized for specific instruction types will contribute to the need for greater diversity in the execution stages. for parallel pipelines there is a strong motivation to implement multiple different execution units –subpipelines in the execution portion of parallel pipeline. we call such pipelines diversified pipelines. ۱۵ ۴۴۷ computer architecture fall ۲ ۸ performance lost due to rigid pipelines instructions advance through the pipeline stages in a lockstep fashion in order …

کلمات کلیدی پرکاربرد در این اسلاید پاورپوینت: ., instruction, pipeline, stage, ۱۵, ۴۴۷, computer, architecture, fall, id, mem, wb,

این فایل پاورپوینت شامل 49 اسلاید و به زبان انگلیسی و حجم آن 1.73 مگا بایت است. نوع قالب فایل ppt بوده که با این لینک قابل دانلود است. این مطلب برگرفته از سایت زیر است و مسئولیت انتشار آن با منبع اصلی می باشد که در تاریخ 2019/05/16 03:06:30 استخراج شده است.

https://web2.qatar.cmu.edu/~msakr/15447-f08/lectures/Lecture15.ppt

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