Minimum cover that is prime

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● Design Technology
● Outline
● Introduction
● Improving productivity
● Automation: synthesis
● The parallel evolution of compilation and synthesis
● Synthesis Levels
● Logic Synthesis
● Two-level minimization
● Cont.
● Minimum cover that is prime
● Minimum cover: heuristics
● Heuristics: iterative improvement
● Multilevel logic minimization
● Example
● FSM synthesis
● Technology mapping
● Register-transfer synthesis
● Behavioral synthesis
● System synthesis
● Cont.
● Verification
● Formal Verification
● Simulation
● Simulation advantages & disadvantages
● Cont…
● Hardware/software co-simulation
● Cont…
● Emulators
● Cont…
● Reuse: intellectual property cores
● Cont…
● Hard/Soft core advantages & disadvantages
● Firm core advantages & disadvantages
● New challenges to processor providers
● IP protection
● New challenges to processor users
● Design process model
● Waterfall method
● Spiral method
● General-purpose processor design models
● Spiral-like model
● Summary
● References

نوع زبان: انگلیسی حجم: 1.57 مگا بایت
نوع فایل: اسلاید پاورپوینت تعداد اسلایدها: 50 صفحه
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گروه موضوعی: زمان استخراج مطلب: 2019/05/17 12:26:54

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عبارات مهم استفاده شده در این مطلب

عبارات مهم استفاده شده در این مطلب

., gate, cover, synthesis, design, minimum, implicant, level, input, logic, state, ‘,

توجه: این مطلب در تاریخ 2019/05/17 12:26:54 به صورت خودکار از فضای وب آشکار توسط موتور جستجوی پاورپوینت جمع آوری شده است و در صورت اعلام عدم رضایت تهیه کننده ی آن، طبق قوانین سایت از روی وب گاه حذف خواهد شد. این مطلب از وب سایت زیر استخراج شده است و مسئولیت انتشار آن با منبع اصلی است.

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عبارات پرتکرار و مهم در این اسلاید عبارتند از: ., gate, cover, synthesis, design, minimum, implicant, level, input, logic, state, ‘,

مشاهده محتوای متنیِ این اسلاید ppt

مشاهده محتوای متنیِ این اسلاید ppt

by hassan al manasrah tamir al zu’bi design technology outline introduction automation synthesis verification hardware software co simulation reuse intellectual property cores design process models introduction system design goals introduction what does design means task of defining system functionality and converting that functionality into physical implementation. convert functionality to physical implementation while satisfying constrained metrics optimizing other design metrics designing embedded systems is hard because of complex functionality millions of possible environment scenarios. ex elevator controller. so many competing tightly constrained metrics. productivity gap as low as ۱ lines of code or ۱ transistors produced per day many possible combinations of buttons being pressed. improving productivity design technologies developed to improve productivity we focus on technologies advancing hardware software view automation synthesis computer program to replace manual design. which made hardware design look like software design. reuse process of using predesigned components. core in the hardware domain. verification task of ensuring correctness completeness of each design step. hardware software co simulation. automation synthesis the parallel evolution of compilation and synthesis synthesis levels logic synthesis two level logic minimization multi level logic minimization fsm synthesis technology mapping register transfer synthesis behavioral synthesis system synthesis and hardware software co design the parallel evolution of compilation and synthesis in the early design was mostly hardware software was fairly simple. software complexity increased with advent of general purpose processor. different techniques for software design and hardware design caused division of the two fields hardware software design fields rejoining both can start from behavioral description in sequential program model software design evolution machine instructions collection machine instructions called program ’s ۱’s . assemblers convert assembly programs into machine instructions due to hard dealing with huge number of ’s ۱’s. compilers translate sequential programs into assembly hardware design evolution interconnected logic gates logic synthesis converts logic equations or fsms into gates register transfer rt synthesis converts fsmds into fsms logic equations predesigned rt components registers adders etc. behavioral synthesis converts sequential programs into fsmds cont. hardware design involves many more dimensions while compilers must generate assembly instructions to implement itself. hardware designer concerned about size power performance and other metrics. synthesis levels gajski’s y chart each axis represents type of description behavioral defines outputs as function of inputs structural implements behavior by connecting components with known behavior physical gives size locations of components and wires on chip board synthesis converts behavior at given level to structure at same level or lower e.g. fsm → gates flip flops same level fsm → transistors lower level fsm x registers fus higher level fsm x processors memories higher level carry ripple adder addition converting logic level behavior to structural implementation by converting logic equations and or fsm to connected gates. combinational logic synthesis two level minimization multilevel minimization fsm synthesis state minimization state encoding logic synthesis represent logic function as sum of products or product of sums and gate for each product or gate for each sum this minimization gives best possible performance when at most we have ۲ gates delay goal minimize size minimum cover minimum cover that is prime two level minimization minimum of and gates sum of products literal variable or its complement a or a’ b or b’ etc. minterm product of literals each literal appears exactly once abc’d’ ab’cd a’bcd etc. implicant product of literals each literal appears no more than once abc’d’ a’cd etc. covers ۱ or more minterms a’cd covers a’bcd and a’b’cd cover set of implicants that covers all minterms of function minimum cover cover with minimum of implicants minimum cover minimum cover k map approach karnaugh map k map ۱ represents minterm circle represents implicant minimum cover covering all ۱’s with min of circles example direct vs. min cover less gates ۴ vs. ۵ less transistors ۲۸ vs. ۴ f abc d a cd ab cd ۲ ۴ input and gate ۱ ۳ input and gates ۱ ۴ input or gate → ۲۸ transistors k map sum of products k map minimum cover minimum cover minimum cover implementation cont. minimum of inputs to and gates prime implicant implicant not covered by any other implicant max sized circle in k map minimum cover that is prime covering with min of prime implicants min of max sized circles example prime cover vs. min cover same of gates ۴ vs. ۴ less transistors ۲۶ vs. ۲۸ minimum cover that is prime minimum cover heuristics k maps give optimal solution every time functions with ۶ inputs too complicated use computer based tabular method finds all prime implicants finds min cover that is prime also optimal solution every time problem ۲n minterms for n inputs ۳۲ inputs ۴ billion minterms exponential complexity heuristic solution technique where optimal solution not guaranteed hopefully comes close heuristics iterative improvement start with initial solution i.e. original logic equation repeatedly make modifications toward better solution common modifications expand replace each nonprime implicant with a prime implicant covering it delete all implicants covered by new prime implicant reduce opposite of expand reshape expands one implicant while reducing another maintains total of implicants irredundant selects min of implicants that cover from existing implicants synthesis tools differ in modifications used and the order they are used multilevel logic minimization trade performance for size increase delay for lower of gates gray area represents all possible solutions circle with x represents ideal solution generally not possible ۲ level gives best performance max delay ۲ gates solve for smallest size multilevel gives pareto optimal solution minimum delay for a given size minimum size for a given delay size delay multi level minim. ۲ level minim. example minimized ۲ level logic function f adef bdef cdef gh requires ۵ gates with ۱۸ total gate inputs ۴ ands and ۱ or after algebraic manipulation f a b c def gh requires only ۴ gates with ۱۱ total gate inputs ۲ ands and ۲ ors less inputs per gate assume gate inputs ۲ transistors reduced by ۱۴ transistors ۳۶ ۱۸ ۲ down to ۲۲ ۱۱ ۲ sacrifices performance for size inputs a b and c now have ۳ gate delay iterative improvement heuristic commonly used converting fsm to gates state minimization reduce of states identify and merge equivalent states outputs next states same for all possible inputs. tabular method gives exact solution. table of all possible state pairs. if n states n۲ table entries. heuristics used with large of states. state encoding unique bit sequence for each state. if n states log۲ n bits to represent n unique encodings. n possible encodings. thus heuristics common. fsm synthesis smaller states registers and fewer gates library of gates available for implementation simple only ۲ input and or gates complex various input and or nand nor etc. gates efficiently implemented meta gates i.e. and or invert mux final structure consists of specified library’s components only if technology mapping integrated with logic synthesis more efficient circuit more complex problem technology mapping converts fsmd to custom single purpose …

کلمات کلیدی پرکاربرد در این اسلاید پاورپوینت: ., gate, cover, synthesis, design, minimum, implicant, level, input, logic, state, ‘,

این فایل پاورپوینت شامل 50 اسلاید و به زبان انگلیسی و حجم آن 1.57 مگا بایت است. نوع قالب فایل ppt بوده که با این لینک قابل دانلود است. این مطلب برگرفته از سایت زیر است و مسئولیت انتشار آن با منبع اصلی می باشد که در تاریخ 2019/05/17 12:26:54 استخراج شده است.

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